Tutorials & Invited


Lessons from Brain Connectivity for Future Interconnect in ICs
Jan Rabaey
University of California at Berkeley - UCB, USA
September 2nd, Wednesday, 08:40 to 09:40
Short Bio: Jan Rabaey received his Ph.D degree in applied sciences from the Katholieke Universiteit Leuven, Belgium. In 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he now holds the Donald O. Pederson Distinguished Professorship. He is currently the scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the founding director of the Berkeley Ubiquitous SwarmLab. Prof. Rabaey has made high-impact contributions to a number of fields, including advanced wireless systems, sensor networks, configurable ICs and low-power design.  His current interests include the conception and implementation of next-generation integrated wireless systems over a very broad range of applications, as well as exploring the interaction between the cyber and the biological world. He is the recipient of a wide range of major awards, amongst which the IEEE CAS Society Mac Van Valkenburg Award, the European Design Automation Association (EDAA) Lifetime Achievement award, and the Semiconductor Industry Association (SIA) University Researcher Award. He is an IEEE Fellow and a member of the Royal Flemish Academy of Sciences and Arts of Belgium, and has been involved in a broad variety of start-up ventures.
Majority-based Synthesis for Digital Nano-technologies
Giovanni de Micheli
EPFL, Switzerland

September 3rd, Thursday, 08:40 to 09:40

Abstract: Logic synthesis/optimization algorithms and tools have been used for over three decades. Still they suffer from various weaknesses, because they were conceived with CMOS AOI static gates in mind, with more primitive computers and storage systems, and without a strong formal basis. The design of large-scale, computation oriented, digital circuits is still a main challenge even with state of the art commercial tools. Because of the convergence of fabrication technologies, the competitive edge in CMOS design resides in its logic-level structuring achieved within synthesis. Moreover, novel nano technologies open new horizons by means of logic gates with enhanced functionality. Thus, more than ever, synthesis technology is a key to exploit technology in the search for the best design. This talk shows the motivation for searching better models and algorithms -  as compared to the state of the art - for logic synthesis. A new Boolean algebra and model is shown to be effective for digital circuit optimization for speed, area and power consumption. Experimental results show that the new tool, MIGHTY, outperforms a commercial tool on the three metrics after complete physical design.
Short Bio: Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering at EPFL. He is program leader of the Nano-Tera.ch program. Previously, he was Professor of Electrical Engineering at Stanford University. Prof. De Micheli is a Fellow of ACM and IEEE and a member of the Academia Europaea.  He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 600 technical articles. He is member of the Scientific Advisory Board of IMEC (Leuven, B), CfAED (Dresden, D) and STMicroelectronics. Prof. De Micheli is the recipient of the 2012 IEEE/CAS Mac Van Valkenburg award for contributions to theory, practice and experimentation in design methods and tools, of the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems, and of other best paper awards.
A Path towards Average-Case Silicon via Asynchronous Resilient Bundled-Data Design
Peter Beerel
University of Southern California (USC) in Los Angeles, USA

September 4th, Friday, 08:40 to 09:40

Abstract: The periodic nature of the global clock in traditional synchronous designs forces circuits to be margined for the worst possible case of process, voltage, temperature, and data conditions. This constrains the silicon to operate at worst-case frequencies and at conservative supply voltages. Resilient architectures promise to remove these margins, by detecting and correcting timing errors when they occur, thereby creating the potential to achieve real average-case operation. However, synchronous resilient schemes previously proposed can suffer from multiple issues, including being susceptible to metastability and requiring complex changes to the architecture to support replay-based recovery from timing errors. These problems respectively lead to circuit failures and/or incur high timing penalties when errors occur. This keynote explores how the research to achieve average-case silicon evolved over the last two decades. Particularly, it discusses a recently proposed asynchronous bundled-data resilient template called Blade that is robust to metastability issues, requires no replay-based logic, and has low timing error penalties. The Author describes some open issues and new research opportunities this template presents, including automation problems to target average-case operation, specific circuit optimizations to minimize resiliency overhead, and the need for new test procedures to tune delay lines and screen out bad chips.
Short Bio: Dr. Beerel received his B.S.E. degree in Electrical Engineering from Princeton University, Princeton, NJ, in 1989 and his M.S. and Ph.D. degrees in Electrical Engineering from Stanford University, Stanford, CA, in 1991 and 1994, respectively. He joined the the Department of Electrical Engineering--Systems at USC in 1994. Dr. Beerel was the Faculty Director of Innovation Studies at the USC Stevens Institute for Innovation from 2006 to 2008 and is currently the Faculty Director of Innovation and Entrepreneurship in Engineering for the Viterbi School of Engineering. He served as Vice-President of CAD and Verification at Fulcrum Microsystems. In May of 2008, he took a leave of absence from USC and co-founded TimeLess Design Automation with one of his Ph.D. students, Dr. Georgios Dimou. They sold the company in July of 2010 to Fulcrum Microsystems, which was acquired by Intel in 2011 and became its Switch Router Division at which he also worked as Chief Scientist, Technology Development. Dr. Beerel's research interests include a variety of topics in CAD and asynchronous VLSI design. He has been a member of the technical program committee for the International Symposium on Advanced Research in Asynchronous Circuits and Systems since 1997, was Program Co-chair for ASYNC'98, General Co-chair for ASYNC'07, is on the Steering Committee, and is General Chair for ASYNC'13.  Dr. Beerel was a recipient of an Outstanding Teaching Award in 1997 and the Junior Research Award in 1998 and the Dean's Faculty Award for Service in 2011, all from USC's School of Engineering. He received a National Science Foundation (NSF) Career Award and a 1995 Zumberge Fellowship. He was also co-winner of the Charles E. Molnar award for two papers published in ASYNC'97 that best bridged theory and practice of asynchronous system design and was a co-recipient of the best paper award in ASYNC'99. He was the 2008 recipient of the IEEE Region 6 Outstanding Engineer Award for significantly advancing the application of asynchronous circuits to modern VLSI chips.

Field Effect Transistor: From MOSFET to Tunnel FET
João Antonio Martino
Universidade de São Paulo - USP, Brazil
September 1st, Tuesday, 08:40 to 10:20
Short Bio: João Antonio Martino was born in Sao Paulo, Brazil in 1959. He received the Electrical Engineering degree from Faculdade de Engenharia Industrial (FEI) in 1981. He received the M.Sc (NMOS Technology) and the Ph.D (CMOS Technology) degrees in 1984 and 1988 respectively in Electrical Engineering (Microelectronics) from University of Sao Paulo (USP), Brazil. He worked as a post-doctoral researcher in joint collaboration between Imec/KUL, Leuven, Belgium and University of Sao Paulo, Brazil from 1989 to 1994 in SOI Technology. He was full professor and head of the Electrical Engineering Department at FEI from 1996 to 2005. He creates and was a head of Post-Graduate Program in Electrical Engineering (Microelectronic) at FEI from 2005 to 2006.  Now he is full Professor (since 2005) and head of CMOS SOI group (since 1990) at Electrical Engineering Department of University of Sao Paulo, Brazil. He was also the head of Electrical Engineering Department at University of Sao Paulo from 2009 to 2013. He is author and co-author of more than 400 technical journal papers and conference proceedings and author/editor of 7 books. He concludes the advisor work of 41 students (16 Ph.D and 25 master students). He introduced the study of SOI devices characterization and technology in Brazil in 1990. His expertise is in the area of the electrical characterization, simulation and modeling of SOI devices at low/high temperatures, strain and radiation environment. He is also interested in SOI-CMOS fabrication process and Multiple Gate devices. He was the head of the first 3D transistor (triple gate FinFET) fabricated in South America in cooperation with UNICAMP and FEI. Recently he is working on Tunnel-FETs in collaboration between University of São Paulo and Imec/Belgium and UTBB SOI (Ultra-Thin Body and Buried oxide) in collaboration with MINATEC, Grenoble. He is Senior Member of IEEE, Member of Electrochemical Society. He has been Chapter Chair of South Brazil Session of IEEE – Electron Device Society (EDS) since 2007 and Distinguished Lecturer of EDS/IEEE since 2008. He is also Vice-Chair of EDS/IEEE Region 9 since 2011 and editor of Region 9 EDS/Newsletter.
Revisiting Diode and Solar Cell extraction methods
Adelmo Ortiz-Conde
Universidad Simon Bolivar, Venezuela

September 1st, Tuesday, 10:40 to 12:20

Short Bio: Adelmo Ortiz-Conde (S’82, M'85, SM'97) was born in Caracas, Venezuela, on November 28, 1956. He received the professional Electronics Engineer degree from Universidad Simón Bolívar (USB), Caracas, Venezuela, in 1979 and the M.E. and Ph.D. from the University of Florida, Gainesville, in 1982 and 1985, respectively. His doctoral research, under the guidance of Prof. J. G. Fossum, was on the Effects of Grain Boundaries in SOI MOSFET’s. From 1979 to 1980, he served as an instructor in the Electronics Department at USB. In 1985, he joined the technical Staff of Bell Laboratories, Reading, PA, where he was engaged in the development of high voltage integrated circuits. Since 1987 he returned to the Electronics Department at USB where he was promoted to Full Professor in 1995.  He was on sabbatical leave at Florida International University, Miami, from September to December 1993, and at University of Central Florida (UCF), Orlando, from January to August 1994, and again from July to December 1998. He also was on sabbatical leave at “Centro de Investigaciones y Estudios Avanzados” (CINVESTAV) National Polytechnic Institute (IPN), Mexico City, Mexico, from October 2000 to February 2001. He has coauthored one textbook, Analysis and Design of MOSFETs: Modeling, Simulation and Parameter Extraction (Springer, 1998, ISBN: 978-0-412-14601-5), over 160 international technical journal and conference articles (including 15 invited review articles). His present research interests include the modeling and parameter extraction of semiconductor devices. Dr. Ortiz-Conde is an EDS Distinguished Lecturer and the Chair of IEEE’s CAS/ED Venezuelan Chapter. He is editor of IEEE Electron Device Letters in the area of Silicon Devices and Technology. He was the Region 9 Editor of IEEE EDS Newsletter from 2000 to 2005. He is a Member of the Editorial Advisory Board of various technical journals: Microelectronics and Reliability, “Universidad Ciencia y Tecnología” and “Revista Ingeniería UC”. He regularly serves as reviewer of several international journals. He has been a member of the Technical Program Committees of a variety of international conferences: Microelectronics Conference (MIEL), International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Symposium on Microelectronics Technology and Devices (SBMICRO),  Design of Circuits and Integrated Systems Conference (DCIS), Latin American Symposium on Circuits and Systems (LASCAS),  and IEEE ANDESCON. He was the General Chairperson of the first IEEE International Caribbean Conference on Devices, Circuits, and Systems (ICCDCS) in 1995, Technical Chairperson of the second, fourth and fifth editions of this conference in 1998, 2002 and 2004  respectively, and the Chairperson of the Steering Committee in 2000.
More , Beyond and More than Moore meeting for 3D
Simon Deleonibus
CEA-Leti, France

September 1st, Tuesday, 13:40 to 15:20

Short Bio: MSc and PhD in Applied Physics from Paris University, in 1979 and 1982 respectively.  Since 2008, he is Chief Scientist (Directeur Scientifique) at LETI watching at the Silicon Technologies Research. From 1999 to 2008, he was Director of the Electronic Nanodevices Laboratory. He managed several Industrial, National and European funded projects.  From 1996 to 1999, he managed the Ultimate CMOS project.  He joined LETI(CEA) in 1986 as a device engineering and process modules development expert for CMOS and Flash memories applications.  He joined Thomson Semiconducteurs (Grenoble) in 1981 as a development and transfer to production process integration engineer.  With his team, he realized the first 20nm gate length MOSFET, world’s smallest transistor in June 1999. He published more than 550 papers. Editor of 1 book (WSPC). Guest editor of 1 Special issue of SSE. Author of 7 book chapters.  He is Editor of IEEE Transactions on Electron Devices. Editor for European Physical Journal - EPJ Applied Physics  He owns 30 patents:  among them the initial patent on contact plug principle, widely used as a standard process by the semiconductor industry.  He is European Chair and Member of the VLSI Technology Symposium(from 2000 to 2006). Member of the 1998 and 1999,2004 and 2005 International Electron Devices Meeting (IEDM) program committtee. Member of the ESSDERC program committee since 2000 and Responsible for the ESSDERC2005 Tutorials. Member of the International Technology Roadmap of Semiconductors(ITRS). Member of the Board of Directors of the Nanosciences Foundation. Member of the European Research Council Engineering Panel. Since 1998, he lectures on microelectronics devices physics and technology  and nanosciences in different Institutions and Universities, in France and Worldwide. Dr. Deleonibus is Fellow of the IEEE . Research Director of French CEA.  IEEE Distinguished Lecturer.  “Chevalier de l’Ordre National du Mérite” Decree of French Presidence .  Recipient of the  “2005 Grand Prix de l’Académie des Technologies - Prix Chéreau Lavet”.  Recipient or co-recipient of 10 Best Papers Awards obtained in International conferences.
Trends and challenges in Nano-electronic technologies for new device concepts
Rita Rooyackers
IMEC, Belgium

September 1st, Tuesday, 15:40 to 17:20

Short Bio: Rita Rooyackers received the degree in industrial chemistry from the Rega Institute for Medical Research, Katholieke Universiteit Leuven (K.U. Leuven), Leuven, Belgium, in 1975, where she followed the basics of VLSI processing of the PMMS program.From 1976 to 1984, she was with the ESAT Lab-oratory, K.U. Leuven, for silicon technology development. In 1984, she joined the newly established research center Interuniversity Microelectronics Center (IMEC), Leuven, where she is currently with the Process Technology Division in the NANO Group, working in the field of vertical and horizontal tunnel FET technology development. She is the co-author of about 100 publications in those fields.
Invited Papers

CMOS-Compatible Spintronic Devices
Siegfried Selberherr
TUWien, Austria
September 2nd, Wednesday, 13:20 to 14:00
Short Bio: Siegfried Selberherr was born in Klosterneuburg, Austria, in 1955. He received the degree of Diplomingenieur in electrical engineering and the doctoral degree in technical sciences from the Technische Universität Wien in 1978 and 1981, respectively. Prof. Selberherr has been holding the venia docendi on Computer-Aided Design since 1984. From 1988 to 1999 he was the Head of the Institute for Microelectronics. From 1998 to 2005 he served as Dean of the Faculty of Electrical Engineering and Information Technology. His current research topics are modeling and simulation of problems for microelectronics engineering.
The smaller the noisier? Low Frequency Noise Diagnostic of Advanced Semiconductor Devices
Cor Claeys
Affiliation: TBD

September 3rd, Thursday, 13:20 to 14:00

Short Bio: Cor Claeys received the Ph.D. degree from KU Leuven in Belgium, where he is Professor since 1990. At imec he is Director Business Growth & Emerging Markets responsible for strategic relations. His main interests are silicon technology, device physics, low frequency noise phenomena, radiation effects and defect engineering and material characterization. He authored and coauthored 14 book chapters and more than 1000 technical papers. He has been the project leader for a large number of projects from the European Commission. He is a Fellow of IEEE and of ECS, and is chair of the Semi Europe ISS committee.
More Moore and More Than Moore meeting for 3D
Simon Deleonibus
CEA-Leti, France

September 4th, Friday, 08:40 to 09:40